datasheet 1 to 4 clock buffer ics551 idt? 1 to 4 clock buffer 1 ics551 rev p 051310 description the ics551 is a low cost, high-speed single input to four output clock buffer. part of idt?s clockblocks tm family, this is our lowest cost, small clock buffer. see the ics552-02b for monolithic dual version of the ics551 in a 20 pin qsop. idt makes many non-pll and pll based low skew output devices as well as zero delay buffers to synchronize clocks. contact idt for all of your clocking needs. features ? low skew (250 ps) outputs ? pb-free packaging ? low cost clock buffer ? packaged in 8-pin soic ? input/output clock frequency up to 160 mhz ? non-inverting output clock ? ideal for networking clocks ? operating voltages of 3.3 and 5.0 v ? output enable mode tri-states outputs ? advanced, low power cmos process ? commercial and industrial temperature versions block diagram q1 iclk q2 q3 q4 output enable
ics551 1 to 4 clock buffer fan out buffer idt? 1 to 4 clock buffer 2 ics551 rev p 051310 pin assignment pin descriptions external components a minimum number of external components are required for proper operation. a decoupling capacitor of 0.01 f should be connected between vdd on pin 7 and gnd on pin 6, as close to the device as possible. a 33 ? series terminating resistor may be used on each clock output if the trace is longer than 1 inch. 1 2 3 iclk 4 q1 q2 vdd q3 gnd q4 8 7 6 5 oe 8 pin (150 mil) soic pin number pin name pin type pin description 1 iclk input clock input. internal pull-up resistor. 2 q1 output clock output 1. 3 q2 output clock output 2. 4 q3 output clock output 3. 5 q4 output clock output 4. 6 gnd power connect to ground. 7 vdd power connect to 3.3 v or 5.0 v. 8 oe input output enable. tri-states outputs when low. internal pull-up resistor.
ics551 1 to 4 clock buffer fan out buffer idt? 1 to 4 clock buffer 3 ics551 rev p 051310 absolute maximum ratings stresses above the ratings listed below can cause perma nent damage to the ics551. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions item rating supply voltage, vdd 7 v all inputs and outputs -0.5 v to vdd+0.5 v ambient operating temperature, commercial 0 to +70 c ambient operating temperature, industrial -40 to +85 c storage temperature -65 to +150 c junction temperature 125 c soldering temperature 260 c parameter min. typ. max. units ambient operating temperature -40 ? +85 c power supply voltage (measured in respect to gnd) +3.0 +5.5 v
ics551 1 to 4 clock buffer fan out buffer idt? 1 to 4 clock buffer 4 ics551 rev p 051310 dc electrical characteristics vdd=3.3 v 10% , ambient temperature -40 to +85 c, unless stated otherwise vdd = 5 v 10% , ambient temperature -40 to +85 c, unless stated otherwise notes: 1. nominal switching threshold is vdd/2. parameter symbol conditions min. typ. max. units operating voltage vdd 3.0 3.6 v input high voltage, iclk v ih note 1 vdd/2+0.7 3.8 v input low voltage, iclk v il note 1 vdd/2-0.7 v input high voltage, oe v ih 2vddv input low voltage, oe v il 0.8 v output high voltage v oh i oh = -25 ma 2.4 v output low voltage v ol i ol = 25 ma 0.4 v output high voltage (cmos level) v oh i oh = -12 ma vdd-0.4 v operating supply current idd no load, 135 mhz 18 ma nominal output impedance z o 20 ? internal pull-up resistor r pu oe 500 k ? input capacitance c in oe pin 5 pf short circuit current i os 50 ma parameter symbol conditions min. typ. max. units operating voltage vdd 4.5 5.5 v input high voltage, iclk v ih note 1 vdd/2+1 5.5 v input low voltage, iclk v il note 1 vdd/2-1 v input high voltage, oe v ih 2vddv input low voltage, oe v il 0.8 v output high voltage v oh i oh = -35 ma 2.4 v output low voltage v ol i ol = 35 ma 0.4 v output high voltage (cmos level) v oh i oh = -12 ma vdd-0.4 v operating supply current idd no load, 135 mhz 35 ma nominal output impedance z o 20 ? internal pull-up resistor r pu oe 220 k ? input capacitance c in oe pin 5 pf short circuit current i os 80 ma
ics551 1 to 4 clock buffer fan out buffer idt? 1 to 4 clock buffer 5 ics551 rev p 051310 ac electrical characteristics vdd = 3.3 v 10% , ambient temperature -40 to +85 c, unless stated otherwise vdd = 5 v 10% , ambient temperature -40 to +85 c, unless stated otherwise notes: 1. with rail to rail input clock. 2. between any 2 outputs with equal loading. 3. duty cycle on outputs will match incoming clock duty cycle. consult idt for tight duty cycle clock generators. 4. with external series resistor of 33 ? positioned close to each output pin. marking diagram (ics551mlf) m arking diagram (ics551mln) parameter symbol conditions min. typ. max. units input frequency 0 160 mhz output frequency 15 pf load, note 4 160 mhz output clock rise time t or 0.8 to 2.0 v 1.0 ns output clock fall time t of 2.0 to 0.8 v 1.0 ns propagation delay note 1 135 mhz 2 4 8 ns output to output skew note 2 rising edges at vdd/2 250 ps parameter symbol conditions min. typ. max. units input frequency 0 135 mhz output frequency 15 pf load, note 4 135 mhz output clock rise time t or 0.8 to 2.0 v 1.0 ns output clock fall time t of 2.0 to 0.8 v 1.0 ns propagation delay note 1 135 mhz 1.5 3 6 ns output to output skew note 2 rising edges at vdd/2 250 ps 551mlf ###### yyww 14 5 8 551mln ###### yyww 14 5 8
ics551 1 to 4 clock buffer fan out buffer idt? 1 to 4 clock buffer 6 ics551 rev p 051310 marking diagram (ICS551MILF) notes: 1. ###### is the lot number. 2. yyww is the last two digits of the year and week that the part was assembled. 3. ?lf? denotes pb (lead) free package. 4. bottom marking: (origin) origin = country of origin if not usa. 551milf ###### yyww 14 5 8
ics551 1 to 4 clock buffer fan out buffer idt? 1 to 4 clock buffer 7 ics551 rev p 051310 package outline and package dimensions (8-pin soic, 150 mil. narrow body) package dimensions are kept current with jedec publication no. 95 index area 1 2 8 d e seating plane a1 a e - c - b .10 (.004) c c l h h x 45 millimeters inches symbol min max min max a 1.35 1.75 .0532 .0688 a1 0.10 0.25 .0040 .0098 b 0.33 0.51 .013 .020 c 0.19 0.25 .0075 .0098 d 4.80 5.00 .1890 .1968 e 3.80 4.00 .1497 .1574 e 1.27 basic 0.050 basic h 5.80 6.20 .2284 .2440 h 0.25 0.50 .010 .020 l 0.40 1.27 .016 .050 0 8 0 8
ics551 1 to 4 clock buffer fan out buffer idt? 1 to 4 clock buffer 8 ics551 rev p 051310 ordering information "lf" suffix to the part number are the pb -free configuration and are rohs compliant. ?ln? denotes parts that are pb free and annealed. while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) assumes no responsibility for either its use or for the infringem ent of any patents or other rights of third parties, which wou ld result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring ex tended temperature range, high re liability, or other extraordina ry environmental requirements are not recomm ended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices o r critical medical instruments. part / order number marking shipping packaging package temperature 551mlf 551mlf tubes 8-pin soic 0 to +70 c 551mlft 551mlf tape and reel 8-pin soic 0 to +70 c 551mln 551mln tubes 8-pin soic 0 to +70 c 551mlnt 551mln tape and reel 8-pin soic 0 to +70 c 551milf 551milf tubes 8-pin soic -40 to +85 c 551milft 551milf tape and reel 8-pin soic -40 to +85 c
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